1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and in particular to semiconductor devices that incorporate strained silicon.
2. Related Technology
The continuous demand for improved performance in electronic devices has been addressed through advances in silicon processing and device technologies that are directed toward reduction in the size of individual semiconductor circuit components. However, economic and physical constraints are making continued reduction of device sizes more difficult, and so alternative solutions for increasing device performance are being sought.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of silicon so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is imparted. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is generally more widely spaced than a pure silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice grow in alignment with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the underlying silicon germanium lattice.
Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 400 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in the mobility of both electrons and holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG. 1. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 10 on which is grown an epitaxial layer of strained silicon 12. The MOSFET uses conventional MOSFET structures including deep source and drain regions 14, shallow source and drain extensions 16, a gate oxide layer 18, a gate 20 surrounded by spacers 22, 24, silicide source and drain contacts 26, a silicide gate contact 28, and shallow trench isolations 30. The channel region 32 of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
While the incorporation of strained silicon in MOSFETs can enhance MOSFET performance, those enhancements are more easily achieved in NMOS devices than in PMOS devices. FIG. 2 shows a graph relating the mobility enhancement of the electrons and holes of a strained silicon layer to the percentage of germanium in a silicon germanium substrate supporting the strained silicon layer. As shown in FIG. 2, a germanium content of 20% produces a significant enhancement of electron mobility but only a slight enhancement of hole mobility. A germanium content of approximately 30% is required in order to achieve significant and approximately equal mobility enhancement for both holes and electrons. However, in practice it is difficult to achieve a strained silicon layer of a useful thickness that is supported on a silicon germanium layer having approximately 30% germanium content. It has been determined that a strained silicon layer has a critical thickness, above which dislocations between the lattices of the strained silicon and the supporting layer, referred to as misfit dislocations, become significantly more likely to occur. Misfit dislocations release the strain imparted to the strained silicon layer and therefore degrade carrier mobility. The critical thickness of a strained silicon layer depends on the amount of tensile strain applied to the silicon lattice, and thus on the germanium content of the underlying silicon germanium layer. For example, it has been determined that a silicon germanium layer having approximately 20% germanium content can support a critical thickness of approximately 200 Angstroms without the risk of significant misfit dislocations, whereas a silicon germanium layer having approximately 30% germanium content can support a critical thickness of only approximately 80 Angstroms. In practical applications, this limitation makes significant enhancement in PMOS devices difficult. For example, it has been determined empirically that a strained silicon thickness of at least approximately 70 Angstroms is required in order to provide a meaningful improvement in NMOS performance. However, in order to account for consumption of the strained silicon layer during processing, a layer of approximately 150 Angstroms must be formed initially, and to avoid misfit dislocation in a layer of that thickness, the germanium content of the underlying layer must be restricted to approximately 20%. While the strain imparted by a 20% germanium content will produce significant carrier mobility enhancement in NMOS devices, PMOS devices incorporating the same strained silicon layer will gain relatively little carrier mobility enhancement. Therefore it is difficult to provide a meaningful application of strained silicon where both NMOS and PMOS devices are to be formed from the same layer of strained silicon. This problem is exacerbated in CMOS devices, where it is highly desirable for the PMOS and NMOS devices to have approximately the same carrier mobility and hence approximately the same drive current so that device speed and performance is not limited to that of the slower type of device. The conventional solutions to this problem in silicon CMOS devices, such as increasing the relative size of the PMOS devices or increasing the drive voltage of the PMOS devices, are equally undesirable in both silicon devices and strained silicon devices because of the greater complexity and size that they entail.
Therefore, while the limiting factors of strained silicon technology can be balanced to achieve improved carrier mobility enhancement in NMOS applications, current technology does not offer a way to impart enough strain to reliably produce comparable carrier mobility enhancements in PMOS devices or CMOS devices.